San Diego, CA; Del Mar, CA
Full-Time $100,000 - $150,000
We are the global leader in a rapidly growing space, working on the most cutting-edge technology available. As a top company in a fast growing industry, we have a great working environment where engineering is our top priority. We manage to keep a vibrant, startup-like environment where innovation and technology advancement occur on a daily basis. You will have the chance to shine as a top contributor and rise the ranks in a growing company while working in an exciting, technology space. The product you will be working on is a next generation product that will revolutionize the data storage space and get a chance to work on the most cutting-edge, modern verification methodologies and environments. We are located in Sunny Southern California in one of the best places to live and work in the world!
If you are a top-notch ASIC Verification Engineer, Senior Design Verification Engineer or Lead Design/Verification Engineer with strong System Verilog experience, please read on!
What's in it for you:
- Working on the latest high-speed technology in a well-known company
- Work with the best and brightest in the industry
- High-visibility and excellent growth opportunity - including the possibility of taking over this group in a lead or management role
- Competitive salary top benefits and stock options
What you need for this position:
- BSEE & 5+ years ASIC Verification experience (MSEE preferred)
- Strong verification with SystemVerilog based OVM / UVM, VMM or related methodology, understanding of interfaces, FIFO's, associative
- High-speed design / verification experience
- Strong background defining cover groups, assertions, coverage driven verification concepts, etc.
- High-level transaction level modeling language experience
- C / C++ & Verilog / VHDL / Logic Design experience
- Emulation experience is a plus
- Verification of multi-power domain designs, ideally using CPF / UPF
- SOC Architecture design and implementation knowledge
- Scripting language experience (i.e. Perl, Shell, Python)
- HW behavioral modeling in SystemC, C/C++, etc is a plus.
What you'll be doing:
- Taking charge of development & deployment of verification methodology
- Developing the verif'n suite using proper verification methodologies and tools
- Planning & execution of system and block level verification
- Working with multi-disciplinary team (design, etc) to meet quality req's at system and block level
- Working with design & architecture teams to understand functionality of logic blocks
So, if you are a top-notch ASIC Verification Engineer, Senior Design Verification Engineer or Lead Design/Verification Engineer with strong System Verilog experience, please apply today!
Must be authorized to work in the United States on a full-time basis for any employer.
Job ID: JK-verifhs
Clicking the green apply button is the best way to apply, but you may also email me your resume in Word:
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Jason Kuna | Recruiting Manager | CyberCoders
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